The present invention relates generally to the field of cache management, and more particularly to arbitration and distribution of data resources to multiple central processing units (CPUs) over a shared bus.
A multi-core processor is a single computing component with two or more independent actual central processing units (CPUs) (i.e., cores), which are the processing units that read and execute program instructions. The instructions are ordinary CPU instructions, such as add, move data, and branch, but the multiple cores allow for multiple instructions to be executed at the same time, potentially increasing overall speed. Manufacturers typically integrate the cores onto a single integrated circuit die, or onto multiple dies in a single chip package. Cores may, or may not, share one or more caches.
A data buffer is a region of a physical memory storage used to temporarily store data while it is being moved from one place to another. Buffers can be implemented in a fixed memory location in hardware—or by using a virtual data buffer in software, pointing at a location in physical memory. Buffers are usually used in a first in, first out (FIFO) method, outputting data in the order it arrived. Buffers can increase performance by allowing synchronous operations, such as reads or writes, to complete quickly, instead of inhibiting performance while waiting for hardware interrupts to access slower memory.
A bus is a communication system that transfers data between components inside a computer, or between computers. A bus may include all related hardware components (wire, optical fiber, etc.) and software, including communication protocols.